Advanced semiconductor chips require enhancement in performance through device performance as well as expanded offering in device types to enable multiple types of devices providing useful functionality. Oftentimes, providing both such enhancement in performance and multiple device types in the same semiconductor chip increases processing costs. Thus, providing as many device types as possible, while limiting processing complexity within reasonable limits, helps provide a highly functional semiconductor chip at a reasonable processing cost.
On one hand, a key performance parameter of advanced semiconductor chips is on-current and off-current of field effect transistors. Typically, high gate leakage current of silicon oxide and nitrided silicon dioxide as well as depletion effect of polysilicon gate electrodes limits the performance of conventional semiconductor oxide containing gate electrodes. High performance devices for an equivalent oxide thickness (EOT) less than 1 nm require high dielectric constant (high-k) gate dielectrics and metal gate electrodes to limit the gate leakage current and provide high on-currents. Materials for high-k gate dielectrics include ZrO2, HfO2, other dielectric metal oxides, alloys thereof, and their silicate alloys.
A high-k dielectric material needs to provide good electrical stability, that is, the amount of charge trapped in the high-k dielectric material needs to remain at a low level even after extended operation of a transistor. The high-k dielectric material needs to be scalable, that is, provide an acceptable level of leakage and acceptable levels of electron and hole mobility at a reduced thickness, e.g., less than 1 nm. High-k dielectric materials satisfying these conditions may be advantageously employed for high performance semiconductor devices.
In general, dual metal gate complementary metal oxide semiconductor (CMOS) integration schemes employ two gate materials, one having a work function near the valence band edge of the semiconductor material in the channel and the other having a work function near the conduction band edge of the same semiconductor material. In CMOS devices having a silicon channel, a conductive material having a work function of about 4.0 eV is necessary for n-type metal oxide semiconductor field effect transistors (NMOSFETs, or “NFETs”) and another conductive material having a work function of about 5.0 eV is necessary for p-type metal oxide semiconductor field effect transistors (PMOSFETs, or “PFETs”). In conventional CMOS devices employing polysilicon gate materials, a heavily p-doped polysilicon gate and a heavily n-doped polysilicon gate are employed to address the needs. In CMOS devices employing high-k gate dielectric materials, two types of gate stacks comprising suitable materials satisfying the work function requirements are needed for the PFETs and for the NFETS, in which the gate stack for the PFETs provides a flat band voltage closer to the valence band edge of the material of the channel of the PFETs, and the gate stack for the NFETs provides a flat band voltage closer to the conduction band edge of the material of the channel of the NFETs. In other words, threshold voltages need to be optimized differently between the PFETs and the NFETs. In some cases, the conventional CMOS devices and metal gate devices may be formed on the same semiconductor substrate to avoid the complexity of processing two types of metal gate materials.
On the other hand, there has been a steady demand for non-volatile memory devices in advanced semiconductor chips. Such non-volatile memory devices include electrically programmable semiconductor fuses and flash memories. Electrically programmable semiconductor fuses provide a secure memory and tends to require a minimal number of additional processing steps in manufacturing, the electrically programmable semiconductor fuses are not erasable, i.e., programmable only once. For this reason, the electrically programmable semiconductor fuses are termed one-time programmable (OTP) memory devices.
Flash memory devices are erasable programmable non-volatile memories. Flash memory devices may store non-volatile information, i.e., the information stored in flash memories are not erased when power is turned off. Unlike electrically programmable semiconductor fuses, information stored in the flash memory devices may be erased and new data may be stored, i.e., the flash memory devices are rewritable. The flash memory devices, however, require a stack of two gate electrodes. As a consequence, additional processing steps are required to form flash memory devices, which increase processing time and processing cost.
In view of the above, there exists a need for a semiconductor structure including a gate stack that may be employed for a flash memory device, a gate stack for a p-type field effect transistor, and a gate stack for an n-type field effect transistor, for the manufacture of which processing complexity and cost are reduced to a minimum.
Further, there exists a need for a method of manufacturing such a semiconductor structure that with minimal processing complexity and cost.